Verilog

Design and Realization of A Translator from Verilog to Java

Verilog到Java翻译器VtoJ的设计与实现

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This paper presents an automatic model compiler, CAMC, which accepts device models in behavioral language, such as Verilog-AMS, and generates C code according to standard circuit simulator programming interface.

本文实现了一个自动化的模型编译器CAMC。CAMC能够接受使用Verilog-AMS等行为级语言描述的器件模型，并按照标准电路仿真器的接口产生C语言代码。

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Research and Realization of Digital Image Sharpening Based on Verilog

基于Verilog的数字图像锐化研究和实现

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The Verilog HDL which is understood easily is adopted for the paper.

系统采用一种软件硬化的设计思路，应用了Verilog hdl硬件语言，该语言较容易理解。

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Our method has advantage in its fine grain, without ( writing-style) ( limitation) ( and) in dealing with more Verilog components characteristics.

与以前的方法相比，该方法的优点是细粒度的、不受书写格式的限制，并且能处理更多Verilog的语法元素。

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We choose a subset of Verilog for our research, which hold the key features of Verilog, including event control, time delay, and concurrency.

选择了Verilog的一个子集作为研究对象，该子集包括了Verilog最重要的语言特征，如事件控制，时延，并发性等；

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The basic principle of PCI bus arbitration and the characteristic of CPLD/ FPGA are described. The design of PCI arbiter based on circular priority algorithm is realized with Verilog HDL. The simulation result is given.

介绍了PCI仲裁的原理，在此基础上描述了基于CPLD/FPGA的一种具有循环优先级通用的PCI仲裁器设计方案，并采用Verilog硬件描述语言设计实现，给出了仿真结果。

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Finally, Verilog HDL hardware language program was written in the FPGA to realize the function of the circuit module and simulated and validated the interpolation algorithm.

最后通过对FPGA编写Verilog hdl硬件语言程序，实现各电路模块的功能以及对插补算法的仿真验证以及实现。

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Finally, on the Verilog implementation of FIR filters, a new structure is presented, with which the speed of the filters are twice the speed with the distributed algorithms.

最后针对FIR滤波器的Verilog实现，提出了一种新型的并串结构，使得滤波器的处理速度是分布式算法的两倍。

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Finally, TAP controller is schemed out by HDL Verilog language, and simulating result of TAP State Machine is gained.

利用硬件描述语言Verilog设计出TAP控制器，得到TAP状态机的仿真结果。

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High Level Design Environment for Digital Integrated Circuit Based on Verilog HDL

基于Verilog HDL的数字集成电路高层设计环境

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This design realizes with verilog hardware describing language, so it has a good flexibility and portability.

本设计采用Verilog硬件描述语言实现, 具有良好的可移植性和设计灵活性.

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We provided a simulation realization of the main memory with Verilog HDL. We also provided a interface to access the external memory chip.

本文提供了外部存储器的一种Verilog语言模拟实现，并提供了对实际存储器件进行访问的访存接口。

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ARM 7 _ verilog source code, after commissioning, is pretty good.

ARM7_verilog的源代码, 经过调试, 很不错.

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UART Receiver Verilog Code complete code can be used directly.

异步接收器Verilog代码完整的源代码可以直接使用.

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In Verilog HDL code , division is improved by quantizing the divisor, which makes hardware realization easy.

在描述硬件过程中,论文对算法中的除法运算进行改进,将除数进行量化处理, 使其更易于硬件实现.

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The design, with Verilog HDL, realizes the IP core on FPGA after the steps of synthesis, placing, routing, functional simulation and timing simulation.

设计使用Verilog语言，对设计的十六位单片机IP进行综合、布局布线、功能仿真和时序仿真后，进行FPGA实现。

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For quality estimate model, it describes the quality factors ( maintainability, reusability etc) and guide lines ( mensurability, readability etc) that imported from Halstead, Mccabe, Verilog metric methodologys.

质量评价模型描述了从Halstead、McCabe的度量方法学和Verilog引入的质量方法学中的质量因素（可维护性、可重用性等）和质量准则（可测试性、可读性等）。

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In this paper, Verilog HDL& a hardware description language is introduced.

介绍硬件描述语言Verilog-HDL。

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In this paper, the semantics of Verilog program are studied in a discrete continuous hybrid time model, a hybrid interval is denoted as the description of a run of Verilog program.

在连续离散混合时间模型中考虑Verilog的语义行为，将混合模型中的一个区间作为Verilog程序一次运行过程的指称。

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The function of circuit was verified by Verilog-XL.

整个电路的功能通过了Verilog-XL 的仿真.

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Verilog HDL coding, functionality and timing simulation for all the module of the digital PLL. 4. Hardware design of the system.

编写Verilog hdl代码，并完成锁相环各个模块的功能与时序仿真。4.详细介绍系统硬件电路板设计。

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Manchester codec Verilog code very good speed, but also occupy less resources.

曼彻斯特编解码Verilog代码非常好的速度快, 而且资源占用少.

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Universal Serial Asynchronous Receiver Transmitter 8251 the Verilog HDL source code, through simulation.

通用串行异步收发器8251的VerilogHDL源代码, 经过仿真验证.

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This article has analyzed the development of real-time image processing system, FPGA technology development present situation, EDA technology characteristic, its development phase and the circuit design flow, Verilog HDL, FPGA/ CPLD characteristic, its programming technology, the structure and the development flow.

本文以实际开发嵌入式系统的流程作为组织文章，布局谋篇的线索。本文分析了实时图像信号处理系统的发展状况，FPGA技术的发展现状。EDA技术特征、发展阶段、电路设计流程；

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This method utilizes and improves the random number generation function provided by verilog to generate a set of random vectors, which approximately obey Gauss distribution. Simulation on the module can be carried out by imitating the real timing of the input signals.

利用Verilog提供的随机数生成函数，并对其加以改进，生成一组近似高斯分布的随机向量，仿效输入信号的真实行为对模块进行仿真。

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According to the results of simulate the test file of digital filter circuit by using Verilog-XL in Cadence. The circuit meets the requests of exact scheduling and correct data.

通过编写测试文件，利用Cadence中的Verilog-XL工具对数字滤波器电路进行仿真验证，电路时序正确，数据无误。

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Verilog HDL design of frequency divider in RTC module is studied here.

文中研究在RTC模块中分频器设计的VerilogHDL实现.

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Detailed introduction data acquisition software realization storage module, namely the key in this paper is an SRAM, reading and writing Verilog HDL realized.

详细介绍数据采集存储模块软件实现是本文的重点，即SRAM读写的Verilog hdl实现。

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Combined with the receiver circuit of SDH network analyzer, transmitter circuit is simulated by NC-VERILOG simulation tools, traversing a variety of TEST_CASE for simulation.

论文构建了具有HARNESS结构的仿真测试平台，利用NC-VERILOG工具，结合SDH网络分析仪接收端电路，对发送端电路进行联合RTL仿真。

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