Verilog的例句大全

According to the results of simulate the test file of digital filter circuit by using Verilog-XL in Cadence. The circuit meets the requests of exact scheduling and correct data.

通过编写测试文件，利用Cadence中的Verilog-XL工具对数字滤波器电路进行仿真验证，电路时序正确，数据无误。

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Design and Realization of A Translator from Verilog to Java

Verilog到Java翻译器VtoJ的设计与实现

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The basic principle of PCI bus arbitration and the characteristic of CPLD/ FPGA are described. The design of PCI arbiter based on circular priority algorithm is realized with Verilog HDL. The simulation result is given.

介绍了PCI仲裁的原理，在此基础上描述了基于CPLD/FPGA的一种具有循环优先级通用的PCI仲裁器设计方案，并采用Verilog硬件描述语言设计实现，给出了仿真结果。

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This method utilizes and improves the random number generation function provided by verilog to generate a set of random vectors, which approximately obey Gauss distribution. Simulation on the module can be carried out by imitating the real timing of the input signals.

利用Verilog提供的随机数生成函数，并对其加以改进，生成一组近似高斯分布的随机向量，仿效输入信号的真实行为对模块进行仿真。

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Verilog HDL coding, functionality and timing simulation for all the module of the digital PLL. 4. Hardware design of the system.

编写Verilog hdl代码，并完成锁相环各个模块的功能与时序仿真。4.详细介绍系统硬件电路板设计。

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The design, with Verilog HDL, realizes the IP core on FPGA after the steps of synthesis, placing, routing, functional simulation and timing simulation.

设计使用Verilog语言，对设计的十六位单片机IP进行综合、布局布线、功能仿真和时序仿真后，进行FPGA实现。

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For quality estimate model, it describes the quality factors ( maintainability, reusability etc) and guide lines ( mensurability, readability etc) that imported from Halstead, Mccabe, Verilog metric methodologys.

质量评价模型描述了从Halstead、McCabe的度量方法学和Verilog引入的质量方法学中的质量因素（可维护性、可重用性等）和质量准则（可测试性、可读性等）。

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Chapter 3 principally analyses the key problems in the design of decoder, which includes RC oscillator, POR ( Power-on Reset), Schmitt trigger, data detect module, model control logic module and data output logic module, then gate simulation is completed by Verilog_XL tool.

本文第三章设计了解码芯片的部分电路模块，包括振荡器电路、上电复位电路、施密特触发器电路、数据检测模块、型号控制逻辑模块、按键防抖动模块以及数据输出逻辑模块。

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Finally, TAP controller is schemed out by HDL Verilog language, and simulating result of TAP State Machine is gained.

利用硬件描述语言Verilog设计出TAP控制器，得到TAP状态机的仿真结果。

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Validation through prototype testing, test results showed that the three-phase locked loop has achieved the synchronization requirements of the PV inverter system and gained a unit power factor for the inverter. Finally, this article used Verilog language to complete the design of FPGA-based three phase-locked loop.

通过样机试验验证，试验结果表明，本文所设计的三相锁相环达到了光伏逆变系统的同步性能要求，实现了逆变器的单位功率因数运行。

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Basod on the power flow analysis of a grid-connected PV system, a solution is provided to implement the control unit of the grid-connected PV system on FPGA using Verilog HDL.

在对光伏并网发电系统的潮流分布进行分析的基础上，给出了基于FPGA的一种光伏并网发电控制系统的实现方案。

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Design and Implementation of the Translator of Verilog HDL to VHDL& VtoV

从Verilog到VHDL的翻译器VtoV的设计与实现

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The design and implementation of a translator from Verilog to VHDL were described.

描述了一个Verilog到VHDL翻译器Verilog2VHDL的设计与实现。

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A Verilog HDL-based Pipelining Design Method and its Application

基于Verilog hdl的流水线的设计方法及应用

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This design realizes with verilog hardware describing language, so it has a good flexibility and portability.

本设计采用Verilog硬件描述语言实现, 具有良好的可移植性和设计灵活性.

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ARM 7 _ verilog source code, after commissioning, is pretty good.

ARM7_verilog的源代码, 经过调试, 很不错.

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Universal Serial Asynchronous Receiver Transmitter 8251 the Verilog HDL source code, through simulation.

通用串行异步收发器8251的VerilogHDL源代码, 经过仿真验证.

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We provided a simulation realization of the main memory with Verilog HDL. We also provided a interface to access the external memory chip.

本文提供了外部存储器的一种Verilog语言模拟实现，并提供了对实际存储器件进行访问的访存接口。

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Finally, Verilog HDL hardware language program was written in the FPGA to realize the function of the circuit module and simulated and validated the interpolation algorithm.

最后通过对FPGA编写Verilog hdl硬件语言程序，实现各电路模块的功能以及对插补算法的仿真验证以及实现。

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In this paper, Verilog HDL& a hardware description language is introduced.

介绍硬件描述语言Verilog-HDL。

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