processor interface的例句大全

This paper proposes a set of common abstraction interface for the micro-processor simulation based on virtual target machine method.

为实现对微处理器的仿真，基于虚拟机（Virtual Target Machine）方法设计出了一组微处理器抽象接口（Abstraction Interface）。

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Abstract This paper introduces the ion pump controller which consist of MC-51 single chip processor and it's interface circuits. It includes ion pump property, major technical function, software and hardware's design and measures taken for the safty of system.

本文介绍了用MC－51单片机及其外国电路组成离子泵智能控制器的特点，主要技术性能，设计指导思想，系统的软硬件设计及对整机可靠性所采取的技术措施等。

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The platform adopted Arm processor to extend thin film transistor liquid crystal display ( TFT-LCD) interface, and acquired the subsystem signals of battery, motor and electric controlling unit by controller area network bus ( CAN-Bus).

采用Arm处理器，扩展薄膜晶体管格式液晶显示器（TFT-LCD）接口，以控制器局部网总线（CAN-Bus）方式，采集电池、电机、电控子系统信号。

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This paper presents the design of Intelligent Bus Control Interface Unit ( IBCIU-B) which is intended to function as a processor/ bus interface in the Digital Avionics Information System ( DAIS).

本文提出了一个适用于数字航空电子信息系统的处理机/总线接口&智能总线控制接口单元（简称IBCIU-B）的设计方案。

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The read-out integrated circuit ( ROIC) is an important interface circuit between infrared focal plane arrays ( IRFPAs) and signal processor.

读出电路是红外成像系统中探测器阵列与信号处理器之间很重要的接口电路。

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In the interactive mode, the commands allow the processor to read/ modify memory areas, set environment variables, download data from the serial port or from the Ethernet interface and execute code routines.

在其交互模式下使用有关命令可以进行对存储区进行读取和修改、设置环境变量、通过串口或以太网接口下载并执行常规代码等操作。

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The thesis have proposed a project of network interface card based on32 ARM processor S3C4510B after analyzing in the MAC layer protocol.

论文在分析了MAC层协议的基础上提出了基于32位ARM处理器S3C4510B的无线网卡设计方案。

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Terminal and host interface processor

终端与主机接口处理器

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An application of Digital Signal Processor ( DSP) in Brain Computer Interface System based on Steady State Visual Evoked Potential ( SSVEP) is presented in this paper. System design and implementation are described in detail, and results of preliminary test are provided.

本文研究数字信号处理器（DSP）在基于稳态视觉诱发电位的脑机接口系统中的应用，同时详细介绍了系统的构成及各部分的设计与实现方法，并展示了初步的实验结果。

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BBL Back-side Bus Logic. Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.

后端总线逻辑。访问内部统一二级处理器缓存的后端总线接口逻辑。

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Finally, compiled interface functions of each module and processor by the software debugging, complete the integrated scheduling of the system, and finally accomplished the study.

最后，利用软件编译环境编写各个模块与处理器的接口函数，从而完成系统功能的集成调度，并进行软件调试，最终完成课题。

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This article introduces a method for simulating JTAG debug communication interface in processor.

介绍了对处理器中JTAG调试通信接口的软件模拟方法。

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Generally, according to different interface type, different interface modules in the digital signal processor and data processor are designed, and there are a large number of modules.

通常，在雷达的信息控制处理中心&信号/数据处理机中针对不同的接口类型，设计相应的接口模块，模块数量较多。

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LNMS is made of log receiver, log processor, report engine, report scheduler, Web Services interface and web application.

整个系统由日志采集、日志分析引擎、报表生成引擎、报表调度、对外接口和前台Web应用程序几个模块构成。

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Data processing module with a close-coupled master-slave dual processors employs a digital signal processor ( DSP) as its data processor and a micro-controller as its I/ O interface processor.

数据处理模块采用主从式紧耦合双处理器结构，分别以数字信号处理器（DSP）作为数据处理机，单片微控制器作为I/O接口处理机；

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take it as an example: you can easily assembly a u disk ( removable hard disk) by selecting embedded processor, memory system and usb interface with corresponding system software and driver program.

例如：可以根据需要，选择嵌入式处理器、存储系统再加上USB接口，裁剪相关的系统软件及驱动软件即可构成一个U盘（移动硬盘）。

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the interface circuits and control arithmetic of rotation transformer and digital signal processor were simplified, saved on dsp time.

可简化旋转变压器和数字信号处理器接口电路和控制算法，节省DSP时间开支。

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have designed the interface of ultrasonic transducers of measuring distance and pulse encoders of sampling velocity which use the dsp as the processor;

设计以DSP芯片为核心的超声波测距传感器和光电脉冲编码器的接口电路；

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according to systems architecture, the a/ d and d/ a interface are both connected to a dsp processor to realize speech signal i/ o channels.

结合CPU两个内核不同的体系结构，在DSP内核上连接A/D，D/A模块实现语音信号I/O通道以及实时实现语音编解码算法；

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8051 processor testing system was designed to test the sample in 16 bits parallel interface.

为测试16bit并行接口，设计了以8051芯片为处理器的测试机；

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