sampling clock

Application of the technology of sampling in different phase in clock circuit realizes maximum 200M equivalent sampling rate of timing analyzer.

在时钟电路中采用分相采样技术，实现了定时分析最高200M的等效采样速率。

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This thesis analyzes some influences on the performances of OFDM digital communications, which include carrier frequency offset, symbol timing offset and sampling clock offset.

分析了载波频率偏差、符号定时偏差和样值频率偏差对OFDM系统性能的影响。

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Of course the sampling clock is itself a digital signal.

时钟本身也是数字信号,也会干扰模拟电路.

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We also use the bootstrap circuit to boost the clock of NMOS sampling switch.

芯片还采用了自举电路对时钟信号进行提升,使得NMOS采样开关 的栅电压跟随输入信号变化.

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Interpolation theory in digital signal processing has application in timing synchronization, which makes the sampling clock independent of the timing control so that timing adjustment is realized completely through digital disposal. The issue of interpolation in timing synchronization is discussed.

论文探讨了数字信号处理中插值理论在定时同步中的应用，它使得接收端的采样时钟独立于定时控制，定时调整完全通过数字处理方法得以实现。

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Following the introduction of the basic principle of OFDM, some nonideal effects on the performance of OFDM systems are discussed, such as carrier frequency offset, symbol timing offset and sampling clock deviation.

本文在简要介绍了OFDM的基本原理、关键技术的基础上，针对同步问题进行了深入研究。首先分析了同步偏差中的频率偏差、符号定时偏差及采样时钟偏差对系统性能的影响。

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Design of High Accuracy Synchronous Sampling Clock in Digital Substations

数字化变电站中高精度同步采样时钟的设计

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Secondly, the effects of carrier frequency offset, sampling clock offset, and symbol timing offset on OFDM signals are exploited.

其次本文分析了符号定时误差、采样时钟偏差、频率偏差对解调信号的影响。针对符号定时同步问题，阐述了利用OFDM帧头训练序列同步的方法；

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Because of the capacitance bottom plate sampling and fully differential structure, the charge injection effect of switched-MOSFET and the clock feed-through effect induced signal error are eliminated. The linearity, signal to noise ratio ( SNR) and conversion-speed of the ADC are improved.

由于采用了电容下极板采样和全差分结构，能够有效地消除开关管的电荷注入效应和时钟馈通效应引起的采样信号的误差，提高模数转换器的线型度、信噪比和转换速度。

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