system clock的例句大全

the simplest way to run cpc is to collect system clock cycles, whose event name is system_clock_cycles, or c.

运行CPC的最简单方式是收集系统时钟周期，其事件名是System Clock Cycles或C。

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One video signal and eight data signals were transmitted complexly without increasing transmission bandwidth and raising system clock.

在没有增加传输带宽、也没有提高系统的工作时钟的情况下，完成传输1路视频信号的同时传输8路数据信号的复合传输。

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To ensure the high speed of the system, in the base of analysis and study algorithms principle, combining the characteristics of DES/ 3DES encryption algorithm, using a fully pipelined design to improve the system clock frequency and throughput.

为了保证系统能够实现高速，本文在分析和研究算法原理的基础上，结合DES/3DES加密算法的特征，采用了全流水线结构设计，提高了系统的时钟频率和吞吐量。

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server operation that causes the target server to synchronize its system clock with the multiserver domain.

服务器作业，使目标服务器将其系统时钟与多服务器域时钟同步。

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This method effectively prevents protraction of shorten of system clock.

该方法能有效防止系统的时钟周期因意外的原因伸长或缩短.

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Audio and video input/ output circuit, Internet interface, power distributing system, system clock circuit, system boot configure circuit and reset circuit have been designed.

设计了音视频输入/输出电路、网络接口电路、电源分配系统、系统时钟网络、系统启动配置电路和复位电路等。

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Study High Precise System Clock Using Global Positioning System Receiver

应用GPS接收板研制高精度系统时钟

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Time consistency solves the problem of distributed simulation system clock synchronization.

时间一致性需要解决分布式仿真系统中各仿真节点的时钟同步问题。

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The other hand, the central node receives the synchronized system clock and trigger signal from the timing signal fiber optic network, which provided by the core module.

另一方面从时序信号光纤网接收核心模块提供的精确同步系统时钟和触发信号，从而同步所控制的子系统。

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The design makes the most of hardware resource Spartan-II chip, and adopts pipeline and parallel mode in order to improve the system clock and decode speed.

为充分利用Spartan-II芯片的硬件资源，编译码器采用了流水线方式与并行方式，并提高了系统时钟频率。

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refer to clock frequency and a single list structure, timer architecture can meet the condition of system clock accuracy, and simultaneously reduce run-time of timer.

借鉴时钟的分频思想，采用单链表结构设计的定时组件可以在满足网关系统其它组件对时钟精度要求条件下，降低系统CPU的占用时间。

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the system use input clock as system clock and use parallel structure in system to provide flexible speed.

全系统采用输入数据的同步时钟作为系统时钟，系统内部采用全并行的方式，以提供灵活的速度。

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Uncheck'System clock uses UTC'and select your time zone.

取消'的系统时钟使用国际标准 ',并选择您的时区.

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Calendar events show up in the system clock , so you never miss an important meeting.

计划日程集成于系统日历之中, 确保您不错过重要事件.

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Data collection module can realize real time receiving and preserving of wave data, wave shape playback, pick up phase parameter by person and computer combination, calibration of system clock, monitor of system operation and alarm function.

数据采集模块可以实现波形数据的实时接收、保存、波形回放、人机结合提取震相参数、系统时钟的校准、对系统运行进行监视以及报警功能；

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Both instructional and functional simulation for the whole VSP show that this motion estimation coprocessor works correctly with other functional components of VSP under the system clock rate up to 80 MHz.

目前，已经通过VSP芯片整体的指令级与功能级仿真与验证。结果表明，当系统时钟为80MHz时，运动估计协处理器与VSP的其它功能部件及指令部件可以有机协调地工作。

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Answer: Check the system clock on the user's computer.

答：检查用户电脑上的系统时钟。

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The OSC provides the system clock signal, it can works under three modes: fixed frequency mode, external clock synchronous mode and idle mode.

振荡器模块提供系统时钟信号，并能实现三种工作模式：固定频率模式、外部时钟同步模式和突发模式。

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In the phase locked loop section, only need to set the bias resister a value according to the required system clock. This chip is very effective in the high speed digital image real time processing system.

该系统的锁相环路部分只需设置一个电阻便可得到相应频率的相位锁定的系统主频，这种芯片特别适合于数字图像高速实时处理中的视频锁相。

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System clock on both the CECs should be set to same date/ time.

两个CEC上的系统时钟应该是相同的日期/时间。

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