system clock的例句大全

First it analyzes the phase rotation and inter-carrier interference of the OFDM sub-carriers caused by the clock frequency deviation, and carries on a deviation test for the trial system which verifies the conclusions of theoretical derivation.

首先分析了时钟频率偏差对OFDM子载波造成的相位旋转和载波间干扰，并针对试验系统进行偏差测试，验证了理论推导的结论。

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Presented the principle of large screen field emission display integrated system based on FPGA control technology which includes the video sampling module, buffer module, clock control module, integrated gray-modulation control module and the integrated row control module.

论述基于FPGA的FED视频驱动显示控制系统的工作原理，包括了视频采集控制模块、缓存模块、时钟控制模块、集成灰度调制控制模块以及行集成控制模块等的FPGA控制技术。

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Finally, based on the realization of the above systems, we built a clock synchronization test platform of networked control system based on ICE. The communication system has been tested clock synchronization to verify its capability.

最后，在实现上述系统的基础上，构建了基于ICE的网络化控制系统的时钟同步测试平台，并对系统进行了时钟同步测试，从而检验了网络通信平台的工作能力。

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The hardware system includes power supply circuit, clock reset circuit, JTAG model building circuit, decoding circuit, memory interface circuit, man-machine interface circuit and numeric control constant-current source interface circuit.

硬件系统主要包括电源电路、时钟复位电路、JTAG仿真接口电路，译码电路、存储器接口电路、人机接口电路、ADC转换电路和数控恒流源接口等。

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In this paper, a clock recovery system that based on phase control technology is studied.

本文设计的锁相环路是基于相位控制技术的时钟恢复系统。

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The net video coder is the core of system and composed of CPU module, power-supply clock module, control module, video/ audio gathering& coding module, and net module.

其中网络视频编码器是系统中的核心部分，主要由CPU模块、电源时钟模块、控制模块、视/音频采集编码模块和网络模块组成。

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In the proposed schemes, the redundant configuration of grandmaster clock using Beidou navigation satellite system, GPS ( Global Positioning System) and atomic clock is discussed.

在应用方案中，讨论了利用北斗卫星定位系统、全球卫星定位系统（GPS）和原子时钟构建最高级时钟的冗余配置方案。

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Real Time Clock plays a very important role in variety of application system.

在各种应用系统中，实时时钟占有相当重要的地位。

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Through the programmable logic device ( PLD), the first-in first-out ( FIFO)'s four precise clock and write enabling signals can be achieved, thus the accuracy of the whole system and flexibility of the time delay are increased.

通过PLD能够得到FIFO4路精确的时钟和读写使能信号，从而提高了整个系统的工作时钟精确度和延时的灵活性。

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This dynamic scaling of the clock speed gives some control in throttling the system to consume less power when not operating at full capacity.

时钟速度的这种缩放可以控制系统在未全力运行时消耗较少电能。

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As the name implies, this governor's goal is to get the maximum performance out of a system by setting the processor clock speed to the maximum level and leaving it there.

顾名思义，此调控器的目标的通过将处理器时钟速度设置为最大级别而实现最大的系统性能。

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Clock study of high speed interleaving/ multiplexing data-acquisition system

高速交替/并行数据采集系统时钟研究

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joint estimation of sampling clock and residual frequency offset of ofdm system based on discrete preamble

OFDM系统中离散导频的采样钟和残留频偏联合估计算法

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In order to solve the contradiction between the lack of passive 3-D navigation resource controlled by our country and the urgent need for the system, in these years, the rubidium clock method, pseudolite method and Loran-C method are developed as augmentation schemes based on Double-Star.

为解决我国目前对自主无源三维导航资源的急需，近年来提出了铷钟法、伪卫星法及Loran-C增强法等多种增强方案。

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the bit serial adder system was chosen over a normal gear system because of the number of gears it takes to make the clock's calculations.

该位串行加法器系统是选择了一个由于齿轮数齿轮系统的正常需要，使时钟的计算。

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the design of main circuit includes system startup and reset, memory assignment and management, interrupt response and management, external bus interface, clock and power control, system development and debugging function.

其中，主体电路设计部分包括了系统启动与复位、内存分配与管理、中断响应与处理、外部总线接口、时钟与电源管理、系统开发与调试功能等内容；

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the time system of daya bay experiment is designed to provide time informations and clock signals for all these 3 stations.

大亚湾实验时间系统是为了给三个探测站提供精确统一的对时信息和时钟信号而设计的。

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design of clock generation and drive circuits in high speed cis system

高速CIS时钟发生电路及驱动电路设计

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the novel context window bit-parallel coding system improves the system performance significantly by reducing the number of clock cycles, and it was verified on fpga.

但上下文窗口开多大为宜呢？系数位编码系统有效减少了编码时钟周期数，并在FPGA上进行了功能验证。

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design and analysis of intelligent temperature control and temperature compensating system of cat for hydrogen clock

氢钟智能温度控制及CAT控制电压自动补偿系统设计与分析

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