phase-locked loop的例句大全

the paper studies digital control scheme of resonance inverter frequency-tracking based on all digital phase-locked loop.

本文主要研究了基于全数字锁相环的谐振型逆变器频率跟踪的数字化控制方案.

互联网摘选

Application of CSL Structure in Intergrated Phase-Locked Loop

CSL结构在集成锁相环中的应用

互联网摘选

An Thyristor Medium-frequency Power Supply Startup Circuit Based on Phase-locked Loop

基于锁相环技术的晶闸管中频电源启动电路

互联网摘选

Time difference counting method and phase-locked loop technology are adopted. A systematic phase-detection function module is designed. High-precision measurement of the phase difference is achieved. 4.

采用时间差计数法和锁相环技术，设计了系统的鉴相功能模块，实现了相位差的高精度测量。

互联网摘选

The phase-locked loop band-pass filter and the logarithmic amplifier is adopted in the circuit to insure the reliability of receiving signal.

电路中采用锁相带通滤波器和对数放大器，保证有效信号的可靠接收。

互联网摘选

Finally, the impedance characteristic of piezoelectricity transducer and the principle of frequency tracking were studied. Software phase-locked loop was used to track self-adapting frequency, and arithmetic of frequency tracking based on change step and dichotomy was presented.

最后，对压电换能器的电抗特性和频率跟踪原理进行研究，采用软件锁相环进行了频率自适应跟踪设计，提出变步进与二分法相结合的频率跟踪算法。

互联网摘选

aiming at the 155mb/ s up-stream velocity of atm-pon system, we design the circuit of the burst-mode optical transmitter. we make the frequency synthesis of the pll ( phase-locked loop) get 155mb/ s clock source.

对于PON系统，针对上行传输速率为155Mb/s时，对突发模式光发射机作了电路设计，在电路设计中采用锁相环频率合成器产生155MHz时钟源系统。

互联网摘选

The new method simplifies the detection circuit as well as improves response speed of the detection algorithm for it does not require phase-locked loop circuit.

该方法不需要锁相环电路，简化了检测电路结构，且提高了检测算法的响应速度。

互联网摘选

5Gb/ s CMOS Monolithic Clock Recovery Circuit Rased on Half-rate Phase-locked Loop

基于半速率锁相环的5Gb/s CMOS单片时钟恢复电路

互联网摘选

Validation through prototype testing, test results showed that the three-phase locked loop has achieved the synchronization requirements of the PV inverter system and gained a unit power factor for the inverter. Finally, this article used Verilog language to complete the design of FPGA-based three phase-locked loop.

通过样机试验验证，试验结果表明，本文所设计的三相锁相环达到了光伏逆变系统的同步性能要求，实现了逆变器的单位功率因数运行。

互联网摘选

Application of Integrated Circuit Phase-locked Loop in Measuring Pulse Duty Factor

IC锁相环在脉冲占空比测量中的应用

互联网摘选

This paper introduced a system to pick up the bit alignment signal of digital phase-locked loop which is programmed in AHDL language and its CPU is CPLD ( Complicated Programmable Logic Device).

现介绍一种用CPLD复杂可编程逻辑器件为控制核心，采用AHDL语言编程实现数字锁相位同步信号提取的方法。

互联网摘选

The digital phase-locked loops with linear variable bits control ( LVBC-DPLL) have the features of fast catch in loop.

线性可变码位控制全数字锁相环（LVBC-DPLL）具有环路捕捉时间快的特点。

互联网摘选

Ameliorating to Track the Series Resonant Frequency of the Ultrasonic Vibration System with Phase-Locked Loop

锁相环跟踪超声振动系统谐振频率的改进

互联网摘选

Realization Method of Software Clock Phase-locked Loop in Radio Remote Unit

射频拉远模块中软件时钟锁相的实现方法

互联网摘选

The Application of Phase-Locked Loop To Frequency Changing Speed Regulation System for Synthetic Fibre Spinning Machine

锁相环路在化纤纺丝机变频调速系统中的应用

互联网摘选

Design of Charge Pump for High-Speed Phase-Locked Loop

高速PLL电路中的电荷泵电路设计

互联网摘选

Behavior Modeling of PLL and Its Application in Video Horizontal PLL Optimized implementation scheme of three phase phase-locked loop based on FPGA

锁相环行为级建模及在视频行锁相中的应用基于FPGA的三相锁相环的优化设计方案

互联网摘选

Chaotic Phenomena of the Sampled Phase-Locked Loop System

采样锁相环系统的混沌现象

互联网摘选

Normally, a phase-locked loop has a very narrow loop bandwidth for good jitter attenuation.

用于光纤传输系统的CRC必须满足抖动要求。如果用简单的锁相环（PLL）来满足这一要求的话，将意味着非常窄的环路带宽和非常小的锁定范围。

互联网摘选