phase lock的例句大全

the design of phase-locking frequency synthesis oscillator with low phase noise

低相位噪声微波锁相频率合成振荡器的设计

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tracking frequency based on frequency multiplication phase-locked and synchronization of multi-period

基于多周期同步和倍频锁相的频率跟踪技术

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Additionally, delay-locked loops usually offer better jitter performance than phase-locked loops.

同时, 延迟锁定回路较锁相回路提供更好的抖动效能.

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Goldstone-mode may condense in the color-flavor-locked ( CFL ) phase matter.

重点介绍色味连锁 ( CFL ) 物质及其中的Goldstone -mode 凝聚现象.

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The source consists of a microwave phase-locked loop and a new type of automatic frequency control circuit. Chief factors to influence spectrum purity of microwave output signal and phase noise are analyzed.

该稳定本振源由一个微波锁相环路（PLL）和一种新型自动频率控制电路（AFC）组成，文中分析了影响微波输出信号频谱纯度和相位噪声的主要因素。

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Self-imaging effects are an important mechanism for phase-locking of laser arrays. The self-imaging cavities include the one with phase corrector ( Lau cavity) and the other one without phase corrector ( Talbot cavity).

利用自成像效应进行半导体列阵激光器锁相是一种重要的外腔锁相技术，所构成的共振腔可分为Talbot腔和带相位补偿板的Lau腔。

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Simple and Practical Formulae of Noise Bandwidth for Sampled Phase-locked Loops

取样锁相环的实用噪声带宽公式

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Realizing High Accurate Measurement by Simulation of the Equivalent Noise Bandwidth of Interferometer Phase-locked Loop

干涉仪锁相环等效噪声带宽高精度测量的仿真实现

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The acquired three-phase voltage signals are used for software phase-locked loop. The phase information combined with the collected current signals to calculate of harmonic and reactive currents.

采集的三相电压信号，用于软件锁相，得到的相位信息结合采集到的三相电流信号共同完成谐波和无功电流的计算。

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The ideas such as digital phase-locked integration, program-mable PID control and variable cycle speed stabilizing criterion etc, are proposed and applied to the design of the control of rotating platform system.

提出数字锁相积分、可编程PID控制及变周期稳速判据等概念，并应用于转台控制器设计。

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Working knowledge of clock synchronization using phase-lock loop ( PLL ).

理解用锁相环 ( PLL ) 实现时钟同步.

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A fast locking phase-locked loops ( PLL ) with a dual-slope phase frequency detector circuit is presented.

文中提出了一种用于高速锁相环的双斜鉴频鉴相器的结构设计.

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Research of a new phase-locked frequency synthesis theory and method

一种新型锁相频率合成理论与方法的研究

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Design and implementation of high-speed low-jitter CPPLL ( Charge-Pump Phase-Locked Loops ) are focused in this thesis.

高速 、低抖动电荷泵锁相环的设计与实现是论文的中心.

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this paper focused on the modelling and parameter design of a period-controlled fully digital phase-locked loop.

研究了一种基于周期控制的逆变器全数字锁相环的建模和参数设计.

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and the working principle of the phase-locked loop.

然后阐述锁相环的工作原理.

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operation theory and realization method of stator-flux-angle in engineering based on digital phase-locked-loop ( pll ) are presented.

就 定子磁 通角工程上的实现方法,提出了数字锁相环法,分析了其工作原理和实现方法.

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article concludes with a phase-locked loop phase noise improvement approach.

文中最后提出了改善锁相环相位噪声的办法.

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we adopted phase-locked loop in order to assure synchronous sampling and accuracy of fft.

系统采用了硬件锁相环技术,来跟踪电网频率的变化,保证采样的同步和傅立叶变换的准确度.

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the paper studies digital control scheme of resonance inverter frequency-tracking based on all digital phase-locked loop.

本文主要研究了基于全数字锁相环的谐振型逆变器频率跟踪的数字化控制方案.

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