memory buffer的例句大全

This setting controls the size of the NSF buffer pool, a section of memory dedicated to buffering I/ O transfers between the NIF indexing functions and disk storage.

这个设置控制NSF缓冲池的大小，后者是用于缓冲NIF索引函数与磁盘存储之间的I/O传输的一部分内存。

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Memory allocated includes buffer pools, locklist, database heap, utility heap, package cache and catalog cache.

分配的内存包括缓冲区池、锁列表、数据库堆、实用程序堆、包缓存和编目缓存。

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The memory parameter tuning involves the configuration of database buffer, data dictionary buffer and cache.

内存参数的调整包括库缓冲区、数据字典缓冲区和缓冲区高速缓存的调整；

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The database buffer pool ( s) area is normally the largest component of the database shared memory.

数据库缓冲池通常是数据库共享内存中最大的一块内存。

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A buffer pool is an area of storage in memory into which database pages ( containing table rows or index entries) are temporarily read and changed.

缓冲池是内存中的一块存储区域，用于临时读入和更改数据库页（包含表行或索引项）。

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For for a large OLTP database, set aside as much as memory as possible for the buffer pool while keeping the system stable.

对于大型OLTP数据库，在保持系统稳定的同时为缓冲池留出尽可能多的内存。

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This paper first describes its memory model and principles, then analyzes the process of buffer overflow attack with an actual example.

文章首先描述了缓冲区溢出攻击的内存模型和产生的原理；然后结合缓冲区溢出漏洞的攻击源代码，分析了缓冲区溢出攻击的实现过程；

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Buffer memory management mechanism of traditional database use data block as the replacement unit, however, any data block contains a large number of other tenants' irrelevant data in shared storage architecture.

传统数据库缓存机制以数据块作为缓存单元，而多租户共享存储架构下，任一数据块均包含了大量其他租户的无关数据，采用数据块作为缓存单元导致大量缓存资源的浪费。

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This design uses two-port Random Access Memory ( RAM) in FPGA as data buffer, so it is very convenient because PCI-E bus and local bus can accesses it though respective port.

为了增加系统的灵活性，在FPGA中设计了双端口随机存储器（RAM）作为数据的缓存区，PCI-E总线和本地总线可以通过各自的接口对其独立的访问。

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The C language allows indirect access memory location by pointer without boundary check, which may cause buffer overflow.

由于C语言允许通过指针进行间接内存访问，但并不进行边界检查，因此可能存在缓冲区溢出。

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The experiment results on FPGA board shows that our memory monitor module can effectively defend majority buffer overflow attacks.

在FPGA板上的实验结果表明该监控模块能够有效防住大部分缓冲区溢出攻击，监控模块带来了5%的硬件开销和0.1%的性能损耗。

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The FPGA is designed as a MVB controller which consists of Manchester encoder, Manchester decoder, buffer, center control unit, internal memory, MCU interface and so on.

FPGA实现MVB控制器功能，分为曼彻斯特编码器、解码器、缓冲区、中央控制单元、内部存储器和单片机接口等几部分。

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DDR SDRAM memory bank is used as the mass buffer in some applications.

本处理板中还加入了一个DDR SDRAM内存条，主要是考虑到实际应用中可能需要大容量缓存。

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And it used the neutral language to compile the information of writing into buffer memory device as the neutral code, in order to realize the goal of communication between the different platform.

并利用中性语言把写入缓存器的消息编译为中性编码，以实现跨平台通讯的目标。

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Conventional attacks generally exploit buffer overflow, double free, integer overflow, format string vulnerability and override somewhere in the memory location to achieve the purpose of changing the control flow.

常规的攻击方式一般利用缓冲区溢出、双重释放、整形错误、格式化输出函数等漏洞，覆写某处内存位置来达到改变控制流的目的，最终实施攻击。

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An Approach to Buffer Overflow Detection Based on Memory Address Confirmation

基于内存地址确认的缓冲区溢出检测方法

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this topic describes how pages of memory from the buffer pool are assigned when using non-uniform memory access (numa).

本主题介绍，在使用非一致性内存访问（NUMA）时，如何分配缓冲池中的内存页。

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it allows you to monitor the sql server buffer pool page distribution for each non-uniform memory access (numa) node.

通过它，您可以监视每个非一致性内存访问（NUMA）节点的SQLServer缓冲池页分布。

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aslr helps prevent buffer overflow attacks by randomizing the location where system executables are loaded into memory.

ASLR通过将系统可执行程序随机装载到内存里，从而防止缓冲区溢出攻击。

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incoming packets are saved to a temporary memory area or buffer in memory.

传入分组保存到临时内存区或内存缓冲区中。

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