In recent years, due to the development of nanometer process technology, various nanostructures fabrication are relatively easy, surface plasmon polaritons have become the focus of scholars' attention.

The latest research advances in tool coating materials, single-coating and multiple-coating, phisical and chemical coating technology, and nano-scale coating technology are investigated and summarized.

文中全面综述了刀具涂层材料、单涂层和多涂层结构、物理和化学涂层工艺、纳米涂层工艺的最新研究进展。

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Based on this framework, some recommended design rules which are fit on the beginning of low yield process in nanometer process are summarized.

基于该设计流程，分析总结了一些纳米级工艺条件下适合在成品率较低的工艺初始阶段应用的可制造性设计规则。

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Intel showed this first look at a transistor built with its32-nanometer manufacturing process.

这表明在与英特尔的32纳米制造工艺生产的晶体管先看看。

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The nano-doping mechanism was investigated based on comparing conventional process with nano-doping process.

根据传统工艺与纳米掺杂工艺的比较，对纳米掺杂机理进行了研究。

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Study on Diameter and Process Relationship of Electrospun PAN Nanofiber

静电纺丝聚丙烯腈纳米纤维工艺参数与纤维直径关系的研究

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As CMOS IC fabrication technology continuously progresses toward nano nodes. The self-aligned silicide ( SALICIDE) material and technology also require corresponding innovations.

随着CMOS集成电路制造技术持续向纳米级工艺推进，与之相应的自对准硅化物（SALICIDE）材料和工艺也在不断的发展创新。

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The affection of the gel concentration, heat treating temperature and time on synthesis of the CoO nanoparticles were studied.

分析了胶体浓度、热处理温度和时间对制备CoO纳米颗粒工艺的影响。

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With the development of deep sub-micron and nanometer CMOS process, it is possible to design and implement millimeter-wave CMOS integrated circuits with low cost.

随着深亚微米和纳米CMOS工艺的成熟，设计和实现低成本的毫米波CMOS集成电路已成为可能。

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Fabrication and Characterization of Controlled Microstructure Photo-Anode for TiO_2 Thin Film by Nano Imprint Lithography

TiO2光阳极有序微结构的纳米压印工艺

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Study on the technology of preparing al_2o_3 nano-powder by wet chemical method in supersonic field

超声场中湿法制备Al2O3纳米粉工艺研究

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The development of traditional processor architecture is restricted by many problems arose in nanometer technology designs, such as power dissipation, wire delay, design complexity, etc. Tiled processor architecture is a potential solution to these challenges.

纳米工艺所带来的功耗、线延迟和设计复杂度等问题制约了处理器体系结构的发展，分片式结构设计是解决这些问题的一种方法。

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However, it has brought more challenges to the reliability of circuits in nanometer technology, one of which is the effect of circuit aging.

但是与此同时，也给数字电路的可靠性问题带了更多新的挑战。纳米工艺条件下，老化是影响数字电路可靠性的主要问题之一。

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However, the description assumed that the critical path delay is Gaussian distribution which is no longer suitable for the nanometer process of next generation.

然而该表述假定关键路径延迟为高斯分布，此假设将不再适用于下一代的纳米工艺。

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Surface flatness measured on40 nm silicon wafers is comparable between the two methods, but our method is better than other published dummy fill methods.

在使用40纳米工艺的晶圆上，基于模型方法得到的表面平坦度与基于规则的填充方法相当，但是比公开的其它填充方法要好。

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On the 65 nm technology node experiment, EPE has been decreased 10% with this method.

通过65纳米工艺节点的实验，表明了该种方法能够减小10%的边放置误差。

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But this nano-engineered cement is at least five years away.

但这种含有纳米工艺的水泥至少还要在五年以后才能问世。

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Tiled Processor Architecture ( TPA), as a many-core architecture design with good scalability, can cope well with challenges such as power consumption, wire delay, design and verification complexity in nano technology.

分片式处理器体系结构（TPA）能够很好地应对纳米工艺代的功耗、线延迟、设计和验证复杂度等一系列问题，是一种具有良好的性能扩展潜力的众核处理器体系结构设计方案。

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Optimized for security and e-commerce applications, the chips will be manufactured at IBM's300-millimeter wafer fabrication plant in East Fishkill, New York, using a90-nanometer process.

这种芯片将在IBM的纽约300毫米晶圆厂使用90纳米工艺生产，专门为安全性和电子商务进行了优化。

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The continuous scaling of CMOS devices to deep nano technology and inexorable reduction in supply voltage greatly challenge technology.

随着CMOS技术发展至深纳米工艺级别，器件尺寸等比例缩小和电源电压持续降低引发了巨大的技术挑战。

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Because all the associations are read-only reference data, an alternative is use lazy fetch and turn on the second level caches on the associations to avoid the N+ 1 problem.

因为所有的关联对象都是只读引用数据，另一种方法是使用延迟抓取，打开这些对象的二级缓存以避免N+1问题。

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