However, it has brought more challenges to the reliability of circuits in nanometer technology, one of which is the effect of circuit aging.

However, the description assumed that the critical path delay is Gaussian distribution which is no longer suitable for the nanometer process of next generation.

然而该表述假定关键路径延迟为高斯分布，此假设将不再适用于下一代的纳米工艺。

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Surface flatness measured on40 nm silicon wafers is comparable between the two methods, but our method is better than other published dummy fill methods.

在使用40纳米工艺的晶圆上，基于模型方法得到的表面平坦度与基于规则的填充方法相当，但是比公开的其它填充方法要好。

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On the 65 nm technology node experiment, EPE has been decreased 10% with this method.

通过65纳米工艺节点的实验，表明了该种方法能够减小10%的边放置误差。

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But this nano-engineered cement is at least five years away.

但这种含有纳米工艺的水泥至少还要在五年以后才能问世。

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Tiled Processor Architecture ( TPA), as a many-core architecture design with good scalability, can cope well with challenges such as power consumption, wire delay, design and verification complexity in nano technology.

分片式处理器体系结构（TPA）能够很好地应对纳米工艺代的功耗、线延迟、设计和验证复杂度等一系列问题，是一种具有良好的性能扩展潜力的众核处理器体系结构设计方案。

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Optimized for security and e-commerce applications, the chips will be manufactured at IBM's300-millimeter wafer fabrication plant in East Fishkill, New York, using a90-nanometer process.

这种芯片将在IBM的纽约300毫米晶圆厂使用90纳米工艺生产，专门为安全性和电子商务进行了优化。

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The continuous scaling of CMOS devices to deep nano technology and inexorable reduction in supply voltage greatly challenge technology.

随着CMOS技术发展至深纳米工艺级别，器件尺寸等比例缩小和电源电压持续降低引发了巨大的技术挑战。

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Because all the associations are read-only reference data, an alternative is use lazy fetch and turn on the second level caches on the associations to avoid the N+ 1 problem.

因为所有的关联对象都是只读引用数据，另一种方法是使用延迟抓取，打开这些对象的二级缓存以避免N+1问题。

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There is no L3 cache per se, but if required by the application, a software developer can utilize all L1 and L2 caches as one5 MB L3 cache.

但没有三级缓存的设置，不过如果应用需要，程序员可以将没使用的一级缓存、二级缓存整合起来作为三级缓存使用。

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However, the increasing number of processors cores on a single chip increases the demand on two critical resources: the shared L2 cache capacity and the off-chip pin bandwidth.

然而，在单芯片上集成越来越多的处理器内核增加了对两个关键资源的需求：共享二级缓存容量和片外引脚带宽。

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A historical data storage scheme by second-phase cache was proposed, which can reduce the burden of real-time system and help to long-term running.

提出基于二级缓存的历史数据转移存储方案，减轻实时系统的负担，有利于采集系统长期稳定运行。

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Chip multiprocessors ( CMPs) combine multiple processors on a single die, typically with private level-one caches and a shared level-two cache.

片上多处理器是指在一个单芯片上集成多个处理器，通常还带私有的一级缓存和共享的二级缓存。

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Note: The above issue resolution is not solvable if we are eagerly fetching the second level cached data in our query.

说明：如果在查询中使用预先抓取来获取二级缓存中的数据时，我们将无法解决上面提出的问题。

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Because it is still safe for batch inserts, you may have to create a separate, dedicated datasource for them.

因为它对批量插入来说还是安全的，所以你可以为批量插入创建单独的专用数据源。最后一个配置项是可选的，因为你可以在会话中显式关闭二级缓存。

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Now let us discuss the issue with the query optimization for the objects which are configured for second level cache.

现在我们来谈谈关于二级缓存的查询优化问题。

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Second level caching of read-only data is the most efficient followed by non-strict read-write on read-mostly data.

只读数据的二级缓存是最有效的，其次是以读为主的数据的非严格读写。

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It ran out of memory frequently due to the session cache and second level cache.

由于会话缓存和二级缓存的原因，系统会频繁地内存溢出。

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Why do we need Second Level Caching?

我们为什么需要二级缓存？

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The second level cache can also cache your query result.

二级缓存也能缓存查询结果。

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If tests based on your network and memory configurations show N+ 1 performs better, you can use batch fetching, subselect fetching or second level cache for further optimization.

如果基于你的网络和内存配置的测试表明N+1性能更好，那么你可以使用批量抓取、subselect抓取或二级缓存来做进一步调优。

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