wire delay

The development of traditional processor architecture is restricted by many problems arose in nanometer technology designs, such as power dissipation, wire delay, design complexity, etc. Tiled processor architecture is a potential solution to these challenges.

纳米工艺所带来的功耗、线延迟和设计复杂度等问题制约了处理器体系结构的发展，分片式结构设计是解决这些问题的一种方法。

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interconnect wire delay questions in deep submicron ic design

深亚微米集成电路设计中的互连线延迟问题

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Tiled Processor Architecture ( TPA), as a many-core architecture design with good scalability, can cope well with challenges such as power consumption, wire delay, design and verification complexity in nano technology.

分片式处理器体系结构（TPA）能够很好地应对纳米工艺代的功耗、线延迟、设计和验证复杂度等一系列问题，是一种具有良好的性能扩展潜力的众核处理器体系结构设计方案。

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Passive wire delay, active delay device which can have a delayed effect to signal were studied and utilized as delay units.

能对信号产生延迟作用的无源延迟导线、有源延迟器件等都曾被作为延迟单元被人们研究和利用。

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the study and resolution ways of ic interconnect wire delay

集成电路互连延迟问题的研究及对策

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