pipelined

A Pipelined RLS Algorithm Based on Square Root Free QR Decomposition

一种基于无平方根QR分解的流水RLS算法

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A Pipelined AD Converter Based on Fully Differentiating Dual-tunnel Sampling/ Holding Circuit

一种全差分双通道采样保持的流水线操作AD变换器

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There are no pipelined delays associated with the part.

该器件无流水线延迟.

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Among the wide variety of analog to digital converter ( ADC) architectures, pipelined and oversampled ∑-Δ converters are the most suitable candidates to meet the needs of current.

在各式各样的模数转换器（ADC）构架中，流水线ADC与过采样∑-ΔADC应用最为广泛。

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The non pipelined approach is as follows: place a load of dirty clothes in the washer.

非流水线操作如以下所述: 把脏衣服放进洗衣机.

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A Novel Out-of-Range Detection Technique for RSD Calibration in Pipelined A/ D Converters

用于流水线模数转换冗余校正的溢出判断技术

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Some Pipelined code, batch number and so on.

有的是流水线代号 、 批号等.

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Microcode Controller of a High-Speed Multifunctional Pipelined Arithmetic Unit

GF-10-12高速多功能运算部件微码控制器

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By adopting special memory format and state information registers, an efficient memory organization method is presented, whose main characteristics include the simplification of the coding-decoding, pipelined data processing, and a significant reduction of read-write memory accesses.

在引入特殊的数据存储格式和状态信息寄存器组的基础上，提出一种高效的存储器管理方法，简化了编解码过程，实现了数据处理的流水线操作，也大大减少了对存储器的读写次数。

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This dissertation investigates the implementation of low cost, high-speed, high-resolution pipelined ADCs for SoC applications in standard CMOS logic process.

本文研究了标准数字CMOS工艺下适于系统集成的低成本高速高精度流水线模数转换器（ADC）的实现。

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A High Resolution Low Power Sample and Hold Module Dedicated to a Pipelined ADC

一个用于流水线模数转换器的高精度、低功耗采样保持电路

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Research on From-to Chart optimizing method based on pipelined production process operating sequence diagram

基于流水线的机器排序优化从至图分析方法操作程序图操作顺序图

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The SAR real-time imaging process is a typical pipelined structure, which includes many complicated algorithms such as FFT.

合成孔径雷达（SAR）实时成像处理是一种典型的流水线结构，要分为很多步骤分开进行处理，并且数据量大，算法复杂。

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a clocking technique used in fpga pipelined designs

一种用于FPGA流水线设计的时钟技术

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The pipelined global shutter capability enables exposure during read-out to reduce motion blur.

该流水线全球快门功能使在读出，以减少运动模糊曝光。

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Then, a no-multiplier, DA based, pipelined DCT hardware architecture is presented.

在此基础上，提出了基于分布式算法的无乘法器全流水线DCT硬件结构。

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the paper describes the principle, design and implement of pipelined digital signal generator based on vme bus.

介绍了基于VME流水线数字信号产生器工作原理、设计与实现过程。

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To ensure the high speed of the system, in the base of analysis and study algorithms principle, combining the characteristics of DES/ 3DES encryption algorithm, using a fully pipelined design to improve the system clock frequency and throughput.

为了保证系统能够实现高速，本文在分析和研究算法原理的基础上，结合DES/3DES加密算法的特征，采用了全流水线结构设计，提高了系统的时钟频率和吞吐量。

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It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits.

PP - 流水线还可以降低流水线电路的时钟树功耗.

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The pipelined approach is much quicker.

流水线操作方法要快得多.

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this information is pipelined down to the page handler through the httpcontext object.

这些信息通过HttpContext对象传递给页面处理程序。

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The novel equalizer utilizes the pipelined architecture to reduce the computational complexity; uses the decision feedback structure of each module to remove the error remaining in the network. Moreover, it can also overcome the unstableness of IIR structure in nature.

该均衡器利用流水线型结构的模块化并行特点来降低计算复杂度；利用每个模块具有判决反馈结构来消除过去的残留在网络中的误差，同时，也能够克服由于本质上IIR结构存在的不稳定性。

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Characteristic of working at high speed stably they are all pipelined.

这些算法都是流水线的,具有高速稳定的特点.

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Graph Process Unit ( GPU) usually adopts a pipelined architecture, and implements some general computer graphics API.

图形处理器（GPU）通常采用流水线体系结构，遵循通用图形接口规范。

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This thesis describes the system design of a high-resolution pipelined ADC.

本文论述了高速高精度流水线结构模数转换器的设计.

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A High-speed , Low-power pipelined 16×16-bit mul-tiplier based on 0.5μ m CMOS Process is designed using Booth encoder , Wallace tree.

提出了一种16×16位的高速低功耗流水线乘法器的设计.

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