memory bus的例句大全

without modifying the architecture of the external memory bus , the mcs51 mcu always occupies the bus.

如果不修改外部记忆体汇流排的架构，MCS51微控制器永远佔有汇流排。

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with smp, all memory access is posted to the same shared memory bus.

对于SMP，所有内存访问都通过一条相同的共享内存总线。

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ram data-side local memory bus

数据侧本地存储器总线

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the processor is connected to physical memory by the memory bus.

处理器通过内存总线连接到物理内存。

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NUMA reduces the contention for a system's shared memory bus by having more memory buses and fewer processors on each bus.

NUMA通过在每个总线使用更多内存总线和更少处理器来减少系统共享内存总线的争用。

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Design of PCI Bus Memory Card Based on CPLD Technology

基于CPLD的PCI总线存储卡的设计

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After analyzing the traffic characteristics of different data transfer channels in detail, we propose a bus scheduling policy based on multi-channel direct memory access ( DMA), and employ it in a single chip real-time audio/ video decoding system.

本文通过详细分析总线上片内外数据通道的特点和数据流量，给出了一种基于多通道DMA的总线调度策略，并将该策略成功运用于单芯片音视频解码系统芯片的总线设计中。

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ISA bus, I/ O port address and memory space allocation are discussed in this paper. The method of interface board designed for user based on ISA bus is introduced in detail, and two examples are given.

本文讨论了ISA总线、IO端口地址和存储器空间分配，详细介绍了在ISA总线基础上设计用户接口板的方法，同时给出了两个具体的例子。

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The address bus specifies the memory locations ( addresses) for the data transfers.

地址总线为数据传输指明内存位置（地址）。

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The microprocessor uses the address bus to locate data stored in memory.

微处理机使用地址总线设定在存贮器中存贮的数据的地址。

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The address bus is used by the processor to select aspecific memory location or register within a particular peripheral.

地址总线被处理器用来选择在特定外设中的存储器地址或寄存器。

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A novel adaptive-offset bus encoding method was presented for reducing the power dissipation of highly capacitive memory address bus.

为了降低大负载地址总线的功耗，提出了一种新的低功耗自适应偏移量总线编码方法。

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The irredundant sorting bus encoding method reduces the power dissipation of highly capacitive memory address bus based on the dynamic reordering of the modified offset address bus lines.

提出了一种新的低功耗非冗余排序总线编码方法，通过对改进的偏移地址线的动态重排以降低具有高负载的地址总线的功耗。

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The memory system of dual channel A/ D automatic acquisition is studied in this paper. Using transceivers and gating controllers, the data bus and address bus of RAM are respectively controlled.

本文研究了双通道A/D自动采集存储系统，利用数据收发器及数据选通控制器分别控制RAM的数据线及地址控制线。

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It also explains the principles of USB ( Universal Serial Bus) communication, the characteristics of its protocol and the DMA ( Direct Memory Access) communication method.

同时也介绍了变压器绕组变形测试仪的通信模块的设计，说明了USB（通用串行总线）通信原理，协议特点，以及DMA通信方式。

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A RELAXATION METHOD FOR PERFORMANCE EVALUATION OF DISTRIBUTED COMMON MEMORY MULTI-BUS MULTIPROCESSOR SYSTEMS The MS ( Message Store) is an additional functional entity in MHS for X.

分布式公用存贮器型多总线多处理机系统性能评估的张弛法文电存贮器（MS）是X。

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This design uses two-port Random Access Memory ( RAM) in FPGA as data buffer, so it is very convenient because PCI-E bus and local bus can accesses it though respective port.

为了增加系统的灵活性，在FPGA中设计了双端口随机存储器（RAM）作为数据的缓存区，PCI-E总线和本地总线可以通过各自的接口对其独立的访问。

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Design of the embedded DSPs' architecture was described at this aspects: bus structure, instruction system, memory system, pipeline and addressing mode, etc.

本文就总线结构、指令系统、存储系统、流水线、寻址方式等几个方面对一个嵌入式DSP处理器μDSP的体系结构设计进行了详细的阐述。

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Underground data collector mainly including power supply module, A/ D converter of pressure module, RS-485 communication of angle module, LCD module, FLASH memory module, alarm module and CAN bus communication module.

井下数据采集器主要包括供电模块、压力A/D转换模块、倾角RS-485通信模块、液晶显示模块、FLASH存储模块、报警模块和CAN总线通信模块。

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In the hardware design, we discuss the connecting of A/ D, memory expansion, bus control, and program boot loader.

硬件设计讨论了基于TI公司的TMS320C31的设计，包括A／D的连接，存储器的扩展，总线的控制，以及程序引导装入功能的实现。

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