Research and Design of Bus Controller Unit in Video Format Conversion Chip

The LLC is composed of CPU and MVB Control Unit, Digital Input and Output Unit, Power Control Unit, Backboard Bus Unit.

逻辑控制模块主要由CPU及MVB控制单元、数字量输入输出单元（DX）、电源控制单元和背板总线单元四部分组成。

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This paper makes research on signals decoding for the speed and position sensor, and also on bus-mastering in a dual-motor distributed driving EV. Resolver, as a position and speed sensor, is basically a rotating transformer.

本课题针对双电机分布式驱动电动车中速度位置传感器信号的处理，以及实施车体稳定性控制的上位机与电机控制器间信息交换开展了研究。

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In the system, the electric executor is applied for the development of bus-mastering system I adopt CAN field bus because its strong interfere resistance capability, high speed communication and small ratio of communication error.

本论文所论述的系统选用抗干扰性强、通信速率高、通信错误率低的CAN总线通信，以适应于总线分布式控制系统的发展。

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Regarding to this, an architecture based on the software bus-mastering is presented and a relevant interface protocol standard is designed.

针对存在的不足之处，提出了基于软件总线控制的体系结构，并设计了相应的接口协议标准。

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The maintaining methods of I~ 2C bus-mastering color TV

冬季女装色彩预测I~2C总线控制彩电的维修方法

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The computer monitoring system based on bus-mastering for heat treatment workshop was introduced and its characteristics and performance were discussed.

介绍了基于总线方式的热处理车间计算机监控系统的构成，论述了该系统的特点及功能。

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Computer Monitoring System Based on Bus-mastering for Heat Treatment Workshop

基于总线方式的热处理车间计算机监控

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Numerical Control Color TV I~ 2C Bus-mastering Technology

新型彩电I~2C总线控制技术

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Application of Field Bus-mastering System in Liquid SO_3 Plant

现场总线控制系统在液体SO3装置上的应用

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B bus is a centralized network with bus topolopy. It is composed of a BC ( Bus Controller), several RTs ( Remote Terminals), and also a MT ( Monitor Terminal).

1553B总线是一种集中式控制的串行总线型网络，其组成包括一个总线控制器、若干远置终端，还可以包括总线监视器。

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RS 485 physical layer standard is applied to build bus topolopy control network, token bus is adopted in this network to realize multiple access in order to meet real-time request of control network.

应用RS485物理层标准，构建总线型的控制网络，采用令牌方式实现总线的共享访问，以适应控制网络实时性要求。

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The Neuron chip is the key part of this module and local bus topolopy heightens the stability and reliability.

本模块以Neuron神经元芯片为核心，采用现场总线拓扑结构进行组网，增强了稳定性和数据传输的可靠性。

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The design we introduced is according to the national standard of GB17945-2000. It's a bus snooping fire emergency Luminarites base on DALI ( Digital Addressable Lighting Interface) protocol.

本文介绍了按照GB17945&2000规定，以DALI协议为通信手段的总线式消防应急灯具的设计。

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By using the technology of the fault converse inference, expert system, bus snooping and so on, the system's reliability and flexibility is greatly enhanced.

该系统以PC/104型工业控制计算机为核心，综合运用故障逆向推理机制、专家技术、总线监测技术等，有效地提高了系统的可靠性、通用性。

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And the architecture of multiprocessors based on shared bus is an advisable architecture. The article has studied the bus arbitration mechanism of multiprocessor system architecture based on the characteristics of modern instrument. We selected the distributed arbiter and dynamic priority scheme to implement the target bus arbiter.

在分析现代仪器系统特点的基础上，研究了多微处理器系统的总线仲裁机制，选择了基于分布式仲裁方式和动态优先权策略作为系统的总线仲裁机制。

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Realize the interface between PCI9054 and the PCI bus, including the bus arbitration, read and write of the registers, the configuration of the EEPROM, the DMA transfer, interrupt response and so on.

实现PCI9054与计算机PCI总线的接口，包括总线仲裁，寄存器读写操作，EEPROM的配置和下载，DMA传输，中断响应等功能。

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The PCB of hardware system is completed under the guidance of high-speed circuit design theory. A new multi-DSP parallel interconnected structure based on bus arbitration is presented, which has the features of simple structure, flexible data transfer and multiple DSPs in equal status.

并在高速电路设计理论指导下完成了系统硬件平台PCB设计。提出了基于总线仲裁的新型多DSP对等全互连结构，该方法结构简单，数据传输灵活，多个DSP地位平等，不分主从。

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The bue CAN has the functions of in polysleeve way, non-destructive bus arbitration technigue, super-strong-error measurement and high communication rate etc. which have been widely used in the various low cost, high anti-interference multi-machine systems.

CAN总线以其多主方式、非破坏性总线仲裁技术、超强错误检测和高通信速率等功能在各种低成本、高抗干扰的多机系统中得到了广泛应用。

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The basic principle of PCI bus arbitration and the characteristic of CPLD/ FPGA are described. The design of PCI arbiter based on circular priority algorithm is realized with Verilog HDL. The simulation result is given.

介绍了PCI仲裁的原理，在此基础上描述了基于CPLD/FPGA的一种具有循环优先级通用的PCI仲裁器设计方案，并采用Verilog硬件描述语言设计实现，给出了仿真结果。

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The simple structure, flexible communication manner, special short frame format and effective bus arbitration technology make CAN bus a new way for highly reliable data transfer in industrial control and measurement system.

CAN总线以其简单的结构、灵活的通信方式、独特的短帧格式、高效的总线仲裁技术，为工业测控系统中高可靠性的数据传送提供了一种新的解决方案。

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