Numerical Control Color TV I~ 2C Bus-mastering Technology

Application of Field Bus-mastering System in Liquid SO_3 Plant

现场总线控制系统在液体SO3装置上的应用

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B bus is a centralized network with bus topolopy. It is composed of a BC ( Bus Controller), several RTs ( Remote Terminals), and also a MT ( Monitor Terminal).

1553B总线是一种集中式控制的串行总线型网络，其组成包括一个总线控制器、若干远置终端，还可以包括总线监视器。

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RS 485 physical layer standard is applied to build bus topolopy control network, token bus is adopted in this network to realize multiple access in order to meet real-time request of control network.

应用RS485物理层标准，构建总线型的控制网络，采用令牌方式实现总线的共享访问，以适应控制网络实时性要求。

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The Neuron chip is the key part of this module and local bus topolopy heightens the stability and reliability.

本模块以Neuron神经元芯片为核心，采用现场总线拓扑结构进行组网，增强了稳定性和数据传输的可靠性。

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The design we introduced is according to the national standard of GB17945-2000. It's a bus snooping fire emergency Luminarites base on DALI ( Digital Addressable Lighting Interface) protocol.

本文介绍了按照GB17945&2000规定，以DALI协议为通信手段的总线式消防应急灯具的设计。

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By using the technology of the fault converse inference, expert system, bus snooping and so on, the system's reliability and flexibility is greatly enhanced.

该系统以PC/104型工业控制计算机为核心，综合运用故障逆向推理机制、专家技术、总线监测技术等，有效地提高了系统的可靠性、通用性。

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And the architecture of multiprocessors based on shared bus is an advisable architecture. The article has studied the bus arbitration mechanism of multiprocessor system architecture based on the characteristics of modern instrument. We selected the distributed arbiter and dynamic priority scheme to implement the target bus arbiter.

在分析现代仪器系统特点的基础上，研究了多微处理器系统的总线仲裁机制，选择了基于分布式仲裁方式和动态优先权策略作为系统的总线仲裁机制。

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Realize the interface between PCI9054 and the PCI bus, including the bus arbitration, read and write of the registers, the configuration of the EEPROM, the DMA transfer, interrupt response and so on.

实现PCI9054与计算机PCI总线的接口，包括总线仲裁，寄存器读写操作，EEPROM的配置和下载，DMA传输，中断响应等功能。

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The PCB of hardware system is completed under the guidance of high-speed circuit design theory. A new multi-DSP parallel interconnected structure based on bus arbitration is presented, which has the features of simple structure, flexible data transfer and multiple DSPs in equal status.

并在高速电路设计理论指导下完成了系统硬件平台PCB设计。提出了基于总线仲裁的新型多DSP对等全互连结构，该方法结构简单，数据传输灵活，多个DSP地位平等，不分主从。

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The bue CAN has the functions of in polysleeve way, non-destructive bus arbitration technigue, super-strong-error measurement and high communication rate etc. which have been widely used in the various low cost, high anti-interference multi-machine systems.

CAN总线以其多主方式、非破坏性总线仲裁技术、超强错误检测和高通信速率等功能在各种低成本、高抗干扰的多机系统中得到了广泛应用。

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The basic principle of PCI bus arbitration and the characteristic of CPLD/ FPGA are described. The design of PCI arbiter based on circular priority algorithm is realized with Verilog HDL. The simulation result is given.

介绍了PCI仲裁的原理，在此基础上描述了基于CPLD/FPGA的一种具有循环优先级通用的PCI仲裁器设计方案，并采用Verilog硬件描述语言设计实现，给出了仿真结果。

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The simple structure, flexible communication manner, special short frame format and effective bus arbitration technology make CAN bus a new way for highly reliable data transfer in industrial control and measurement system.

CAN总线以其简单的结构、灵活的通信方式、独特的短帧格式、高效的总线仲裁技术，为工业测控系统中高可靠性的数据传送提供了一种新的解决方案。

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Performance and bus arbitration for DMA can be found in "DAB, DCB, and DEBPerformance" on another page.

DMA的性能及总线仲裁在其他页面的“DAB，DCB和DEB性能”中可以找到。

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On ATM side, both polling and priority control are used to perform cell bus arbitration. So the QoS control is provided and the cell transfer efficiency is enhanced.

ATM侧利用轮询和优先级控制共用来实现信元总线仲裁，从而实现业务服务质量控制，并提高信元传输效率。

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PC and DSP exchange data using high speed static RAM and bus arbitration circuit and corresponding handshake signal is designed to ensure the correct reading and writing RAM.

PC与DSP的数据交换采用高速静态RAM，并设计总线仲裁电路及相应的握手信号，以保证PC与DSP双方对RAM的正确读写。

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Further investigation on the layered structure, frame form, error detection, node fault confinement, bus arbitration and bus synchronization of CAN is then launched.

然后对CAN总线的分层结构、帧格式、错误检测机制、节点故障界定机制、总线仲裁机制以及总线同步机制进行了深入研究。

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The implemented DSP chip includes test circuits and various peripherals, such as DMA, bus arbitration, timer, and so on.

整个DSP芯片包括测试电路和各种外围设备，如DMA、总线仲裁、定时器等等。

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The scheduling policy of the bus arbitration unit was been analyzed and the I/ O function of RTOS was partly implemented in hardware.

本文在分析总线仲裁单元的时间片调度的基础上，将操作系统的I／O管理的功能部分采用硬件实现。

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Practical application shows that the bus arbitration logic mentioned above is characteristic of low arbitration overhead, fine scalability and higher reliability.

实际运行表明：该仲裁逻辑电路具有仲裁开销小、扩缩性好、可靠性高等特点；

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The user-defined cell structure and cell bus arbitration are put forward, which can sustain the cross connection and series connection.

论文提出了一种自定义的信元结构，信元总线仲裁方式，这种信元总线交换技术支持设备的级联和交叉连接。

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