demultiplexer

The fabrication process of a compact planar waveguide etched demultiplexer based on silicon-on-insulator ( SOI ) is studied.

研究了基于绝缘材料上的硅 ( SOI ) 材料的平面波导刻蚀光栅分波器的主要制作工艺.

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Optimized parameters of the optical configuration of holographic wavelength demultiplexer ( HWD) have been obtained with aberration balancing.

本文用像差平衡的方法求出优化的全息分路器光路结构参量。

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A grating multiplexer and a grating demultiplexer with a channel spacing of 2 nm and a capacity of 18 channels are employed in the system.

系统使用了具有18个频道的能力且频道间隔为2nm的光栅合、分波器，作为波分复用和解复用器。

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Flip-flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. In this thesis we place emphasis on the design of SCFL latches.

触发器是分接器的基本组成单元，建立时间和保持时间是影响电路速度的关键，所以减小建立时间和保持时间是触发器设计的主要目标，本文着重介绍了SCFL锁存器的设计和优化方法。

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Drag onto the page to add a 4-channel multiplexer or demultiplexer.

拖到绘图页后,可以添加4信道多路复用器或信号分离器.

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Design of the concave grating based demultiplexer with a flattened spectral response

凹面光栅型解复用器的通带平坦化设计

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Drag onto the page to add a 2-channel multiplexer or demultiplexer.

拖到绘图页后,可以添加2信道多路复用器或信号分离器.

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In this paper, we introduce the design and implementation of digital interface for power line carrier digital multiplexer demultiplexer.

这里重点介绍数字复接设备中数据接口的设计方案。

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Considering the AWG on SOI we analyze how to reduce its polarization insensitive by using special waveguide structure. We also calculate a 16 channel, 0.8 nm spacing AWG demultiplexer. The results show that the polarization insensitive is less than 0.06 nm.

本文针对SOI材料的阵列波导光栅，分析了如何采用特殊的波导结构来减小它的偏振相关性，并对16通道、间隔为0.8nm的AWG解复用器进行了计算，结果表明其偏振敏感性低于0.06nm。

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The E1 multiplexer which the dissertation focuses on is a subsystem of the 2.5G terminal multiplexer ( the specific demultiplexer of SDH).

本文所研究的E1映射复用模块，是2.5G终端复用器（SDH专用分接器）的一个子系统，它所实现的功能就是从STM-1中分接出E1信号以及把E1信号复用进STM-1。

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design of a flat-field edg wavelength demultiplexer using a two stigmatic points method

两点法设计平场型EDG波分复用器件

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Implementation of Channel Estimation and Demultiplexer with FPGA in DRM

基于FPGA的DRM接收机信道估计与解复用实现

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In this paper, two key technologies in on-board reception digital beamforming network are studied, including digital orthogonal down converter and digital demultiplexer.

本文主要研究星上接收数字波束形成网络中的两项关键技术：数字正交下变频和数字分路。

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Drag onto the page to add a 8-channel multiplexer or demultiplexer.

拖到绘图页后,可以添加8信道多路复用器或信号分离器.

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By optimal design of a multimode interferometer ( MMI) coupler in the input-side, a flattop 32 channels 50 GHz spaced arrayed-waveguide grating ( AWG) demultiplexer was designed and fabricated.

根据优化输入端多模干涉器（MMI）结构设计，研制出32通道50GHz通道间隔、顶部平坦化的阵列波导光栅（AWG）器件。

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In digital demultiplexer, when the number of frequency bands is equal to decimation ratio, the structure of polyphase filter is efficient and easy to be realized. However, its application scenario is limited.

在数字分路中，当抽取倍数等于频带数目时，多相滤波器结构高效且易于实现，但是应用范围有限。

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High-Speed All-Optical Time Division Demultiplexer

高速全光型时分解复用器

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Thirdly, a flat-field EDG demultiplexer is designed to ease the fabrication and packaging.

3 、 设计了平场型EDG器件,简化了制作工艺.

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Design of multi-channel digital signal multiplexer/ demultiplexer based on FPGA

基于FPGA的多路数字信号复分接器的设计

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Adds a multiplexer , demultiplexer, or a similar device to your network diagram.

在网络图中添加多路复用器 、 信号分离器或类似设备.

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Experimental study on long period fiber grating applied in two channel wavelength division demultiplexer

双信道解复用长周期光纤光栅的实验研究

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