1、

DC gain is 80 dB, unity gain bandwidth is 100 KHz, and the phase margin is 90 °. Floating gate current source is introduced to make the circuit more compact. The area of this design is less than 600 100 square microns.

直流增益大于80dB,单位增益带宽积为100K,相位裕度为90°。浮栅电流源的引入使得本文设计的电路结构更紧凑,面积小于600100平方微米。

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2、

Clearly, the pressure drop out of the gate current unfavorable impact of the shutdown GTO.

显然, 这个压降对抽出门极电流不利,影响GTO的关断.

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3、

Gate Current for MOSFETs with High k Dielectric Materials Theoretical Modeling of Gate Current Distribution in MOSFET

高k栅介质MOSFET的栅电流模型(英文)MOSFET栅电流分布的理论建模

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4、

The thyristor can be trigged into the on-state by applying a pulse of positive gate current for a short duration provided that the device is in its forward blocking state.

如果是处于正向阻断状态,只要在门极提供一个短暂的正脉冲,晶闸管就会导通。

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5、

A New Direct Tunneling Gate Current Model for Short Channel MOSFETs with HALO Structure

一个适用于短沟HALO结构MOS器件的直接隧穿栅电流模型

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6、

The RTD has a room temperature peak-to-valley ratio of 5.2 ∶ 1 with a peak current density of 22.5kA/cm2.The HEMT has a 1 μ m gate length with a-1V threshold voltage. A logic circuit called a monostable-to-bistable transition logic element ( MOBILE) circuit is developed.

RTD室温下的峰谷电流比为5.2∶1,峰值电流密度为22.5kA/cm2.HEMT采用1μm栅长,阈值电压为-1V.设计电路称为单稳态-双稳态转换逻辑单元(MOBILE)。

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7、

Due to high read current and complete immunity from over-erase, SST split-gate flash memory has gained a lot attention in both stand-alone and embedded nonvolatile applications.

由于具有高的读电流以及完全避免过擦除的能力,SST分离栅结构超闪存无论是在单体或嵌入式应用方面都得到了人们很多关注。

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8、

The thin film thickness of SOI Groove gate MOS devices affects the threshold voltage, sub-threshold slope and saturation driving current severely. So, it's a very important factor for good device characteristics to optimize the thin film thickness.

仿真结果显示硅膜厚度对SOI槽栅MOS器件的阈值电压、亚阈值特性和饱和驱动能力都有较大影响,选择最佳的硅膜厚度是获得较好的器件特性的重要因素。

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9、

Then the all basic-circuits are also designed and simulated carefully including active resister, current mirrors, comparator, inverter, AND gate, OR gate.

其次对集成电路内所需要的基本模拟及数字电路如有源电阻、电流镜、电压比较器、与门及或门进行了设计和仿真。

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11、

The results show that while the gate biases are more negative, the Schottky depletion layer is thicker and the source-drain current flow is lower.

数值模拟结果表明,器件栅极电压越负,肖特基结的耗尽层越厚,源漏电流越小;

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12、

Study on Thermal Stability and Tunneling Current of Ultrathin Gate Oxidation

超薄栅氧化层的热稳定性和隧道电流研究

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13、

The main trough of riverbed was deepened by large discharge of the river while silted near the river mouth because the sand brought by current deposited near the mouth after closing the water gate.

经过大流量冲刷,河床主槽加深,但在下游水闸关闭后,水流携带的泥沙在下游沉积,出口附近河床反而出现淤积;

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14、

current situation of hot-runner molder of hot valve gate spear system in foreign countries

国外热阀浇口式探针系统热流道模具现状

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15、

For the source/ drain and gate electrodes with an overlap, the structure with SiO2 interfacial layer between high-k gate dielectric and substrate is quite effective for increasing the drive current.

对于源漏和栅堆叠的器件,在高k栅介质和硅衬底间增加SiO2界面层,随着SiO2厚度的增加,驱动电流增加。

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16、

From the gate charge curve ( V_ GS-Q_G), many parameters can be obtained, such as the capacitances of the device, drive current requirements, the power dissipation and so on.

通过栅电荷曲线(VGS-QG),能导出器件的电容特性,驱动电流大小及能量损耗等相关参数。

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17、

Because at that time the gate oxide thickness is already very thin ( 20 A), the tunnel leakage current through mechanism has play a leading role.

因为这时候栅氧化层的厚度已经很薄(20A),栅极漏电流中的隧道穿透机制已经起到主导作用。

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18、

luminescence intensity increased, but the role of the gate voltage to control current is not ideal.

器件的发光强度有所提高,但栅压对载流子的控制作用不理想。

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19、

the emission current density at the apex was found to be the highest, depending exponentially on the gate voltage.

电流密度在纳米线顶端边缘处最大,而且随着栅极电压的增加而呈指数增加。

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20、

the appropriate spectrum for 6 a peak drain-current, 13 v gate voltage and 380 v drain-source voltage has been chosen as reference.

为在峰值6安培漏极电流下获得适当的频谱,选择13伏特的栅源极电压和380伏特的漏源极电压为参考。

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