feature size的例句大全

with the rapid development of integrated circuit ( ic) technology, the feature size of transistors has advanced to the deep submicron, or even ultra-deep submicron ( nanometer) level.

随着集成电路（IC）技术的迅速发展，晶体管的特征尺寸已进入深亚微米、甚至超深亚微米（纳米）级。

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your asic will be based on older processes ( the polite word is" mature"), with a larger feature size.

ASIC基于较老的（礼貌一点说是“成熟的”）处理方式，有效尺寸更大一些。

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with the boost and development of large scale integrated circuit ( lsi), the integration is getting higher and the minimum feature size is shrinking sharply.

随着大规模集成电路的推进和发展，集成度要求越来越高，特征尺寸急剧减小。

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the photonics devices based on the photonic crystal waveguides have a expensively promising application in photonic integration circuits ( pics) because of the high transmission efficiency and small feature size.

光子晶体波导由于具有导光高效和尺寸微小等特性，使得基于它构建的光子学器件在光集成回路中有着广泛的应用前景。

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as the feature size of integrated circuit reaching sub-micron, deep sub-micron and even very deep sub-micron, the parameter extraction and optimization in tcad design are becoming more and more important.

随着集成电路特征尺寸进入小尺寸量级，TCAD设计阶段中的参数提取及优化工作显得更为重要。

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in terms of applying smaller feature size, it enables to drop power dissipation while the highest cut off frequency being constant.

可以通过采用更小特征尺寸，在保持最高截止频率不变的情况下，降低器件的功耗。

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relationship of mask feature size with ope in photolithography

光学邻近效应与掩模特征尺寸的关系

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and the dependence of low-energy neutron-induced seu cross section on sram's feature size was given.

研究结果表明：SRAM器件的特征尺寸越小，其对低能中子导致的单粒子翻转的敏感性越高。

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with the increasing integration of the device, the device feature size is required to decrease rapidly, which means higher demands for the interconnect materials inside the device.

随着器件的集成度越来越高，要求器件的特征尺寸也在迅速减小，这对于器件内部互连线的材料提出了很高要求。

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The feature size is reduced to nano-technology when the chip speed and integration continues to increase.

当工艺特征尺寸减小到纳米的时候，芯片的速度和集成度不断提高。

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as an open platform a model between underlying circuit and architecture level, multi-metrics model can fast and efficiently estimate cache area, latency and power consumption based on different feature size and structural parameters.

作为链接结构模型和底层电路实现与工艺的开放平台，多尺度模型能够依据不同的工艺标准以及结构参数对缓存的面积、延迟、功耗进行快捷而有效地估算。

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power management is an essential part of the electronic system and is moving in the direction of high integration with the continuously shrinking of the feature size and the rapid development of system-on-chip ( soc).

电源管理是电子系统不可或缺的一部分，随着工艺尺寸的不断缩小，片上系统的迅速发展，它也在朝着高集成化的方向发展。

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with the advent of novel materials, structures and devices, the feature size of integrated circuits keeps scaling down, and the moore's law still works.

新材料、新结构、新器件不断涌现，特征尺寸继续缩小，摩尔定律仍然起作用。

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in the deep submicron vlsi circuits, with the feature size scaled down and device density increased, parasitic parameter extraction has become one of the research focuses in the field of electronic design automation.

随着VLSI电路集成密度急剧增长及特征尺寸不断缩小，互连寄生参数提取已成为集成电路辅助设计中的一个研究热点.目前，三维互连寄生电容提取的研究得到广泛关注，并取得了很大进展。

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trends of lithography technology based on decreasing of the feature size

从特征尺寸的缩小看光刻技术的发展

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analysis to the relationship of feature size, objects scales, image resolution

地物大小、对象尺度、影像分辨率的关系分析

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study on correlation of loose aquifer feature size and electric logging parameters

松散含水层特征粒径与电性测井参数的相关性研究

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based on the consideration of feature size, the design concept of ridges and meshes was suggested.

提出了基于最小特征尺寸考虑的脊基和隙空的设计概念。

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the relation between ablated feature size of thin films and femtosecond laser parameters is discussed in details.

本文主要研究分析了刻蚀产生的线宽与激光功率、加工速度、扫描次数、显微物镜数值孔径之间的关系。

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with the continuous decreasing of cmos feature size, it has been possible to realize gbps circuits in cmos technology.

随着CMOS工艺特征尺寸的不断缩减，已经有可能利用CMOS设计Gbps速率等级的电路。

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