higher priority projects usually get their requests answered first.

in the deep submicron vlsi circuits, with the feature size scaled down and device density increased, parasitic parameter extraction has become one of the research focuses in the field of electronic design automation.

随着VLSI电路集成密度急剧增长及特征尺寸不断缩小，互连寄生参数提取已成为集成电路辅助设计中的一个研究热点.目前，三维互连寄生电容提取的研究得到广泛关注，并取得了很大进展。

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as the feature size of integrated circuit reaching sub-micron, deep sub-micron and even very deep sub-micron, the parameter extraction and optimization in tcad design are becoming more and more important.

随着集成电路特征尺寸进入小尺寸量级，TCAD设计阶段中的参数提取及优化工作显得更为重要。

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power management is an essential part of the electronic system and is moving in the direction of high integration with the continuously shrinking of the feature size and the rapid development of system-on-chip ( soc).

电源管理是电子系统不可或缺的一部分，随着工艺尺寸的不断缩小，片上系统的迅速发展，它也在朝着高集成化的方向发展。

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as an open platform a model between underlying circuit and architecture level, multi-metrics model can fast and efficiently estimate cache area, latency and power consumption based on different feature size and structural parameters.

作为链接结构模型和底层电路实现与工艺的开放平台，多尺度模型能够依据不同的工艺标准以及结构参数对缓存的面积、延迟、功耗进行快捷而有效地估算。

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with the rapid development of integrated circuit ( ic) technology, the feature size of transistors has advanced to the deep submicron, or even ultra-deep submicron ( nanometer) level.

随着集成电路（IC）技术的迅速发展，晶体管的特征尺寸已进入深亚微米、甚至超深亚微米（纳米）级。

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the photonics devices based on the photonic crystal waveguides have a expensively promising application in photonic integration circuits ( pics) because of the high transmission efficiency and small feature size.

光子晶体波导由于具有导光高效和尺寸微小等特性，使得基于它构建的光子学器件在光集成回路中有着广泛的应用前景。

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micro-injection molding is a technology which refers to produce components or micro-structures with a feature size ( at least in two dimensions) at a sub-millimeter by injection.

做注塑成型是指以注射的方法生产特征尺寸（至少在二维方向上）处于亚毫米量级的零件或结构的工艺技术。

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personalized mannequins are got through human deformation driven by feature size and curve of human body. a 2d human body feature region and feature parameters extraction method based on user image is proposed.

提出基于图像的二维人体特征区域和特征参数提取方法。

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following enhanced process technology, as the feature size of device decreases, the storage ability of otp increases continually, and at the same time, its performance has improved dramatically.

随着工艺水平不断提高，器件特征尺寸不断减小，OTP存储器在不断增大容量的同时其性能也在不断改善。

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the deformation of surface for shoe-last based on feature size driving is a method that carries on the parameterizations of the model-driven deformation by the extracted feature size.

基于特征尺寸驱动的鞋楦曲面变形以提取的特征尺寸驱动模型进行参数化变形。

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the use of oxide-isolation bipolar process and a feature size of 3 μ m render to the transistor an ft of 3.5 ghz.

采用氧化物隔离双极工艺，最小特征尺寸为3μm，晶体管的f T为3.5GHz。

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interconnect has become a key factor in determining the performance of the integrated circuits with the rapid increase of the signal frequency and the decrease of the feature size of vlsi.

随着信号频率的不断提高和集成电路特征尺寸的不断缩小，互连线已成为决定集成电路性能的主要因素。

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with the advent of the era of deep sub-micron ic, the feature size on the ic chip is shrunk to nanometers.

伴随着深亚微米集成电路时代的来临，芯片的特征尺寸已经缩小到纳米尺度。

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with the advent of novel materials, structures and devices, the feature size of integrated circuits keeps scaling down, and the moore's law still works.

新材料、新结构、新器件不断涌现，特征尺寸继续缩小，摩尔定律仍然起作用。

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with the increasing integration of the device, the device feature size is required to decrease rapidly, which means higher demands for the interconnect materials inside the device.

随着器件的集成度越来越高，要求器件的特征尺寸也在迅速减小，这对于器件内部互连线的材料提出了很高要求。

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with the boost and development of large scale integrated circuit ( lsi), the integration is getting higher and the minimum feature size is shrinking sharply.

随着大规模集成电路的推进和发展，集成度要求越来越高，特征尺寸急剧减小。

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and the dependence of low-energy neutron-induced seu cross section on sram's feature size was given.

研究结果表明：SRAM器件的特征尺寸越小，其对低能中子导致的单粒子翻转的敏感性越高。

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the purpose of study is to reduce feature size on the adverse impact. one method is by introducing new materials, especially the improvement of gate material.

研究的目的就在于降低特征尺寸减小所带来的不利影响，方法上可以从器件制作的材料入手，引入新型材料，特别是栅材料的改良。

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the trend of scaling down of ic feature size day by day leads to inevitability of developing flash memories technology of next generation.

集成电路工艺特征尺寸的日益缩小趋势使得寻找下一代快闪存储器技术成为必然。

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then the smaller feature size of spout holes is achieved by micro-edm with layer-by-layer scan machining.

型孔喷口的最小特征尺寸采用微细电火花逐层扫描加工得到。

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